In semiconductor integrated circuits, power supply noise which appears as a result of the operation of a circuit section around a clock path may have an influence on the clock path and clock jitter may occur in a transmitted clock signal. A technique for calculating clock jitter which occurs due to power supply noise and a technique for designing a semiconductor integrated circuit with calculated clock jitter taken into consideration are known.
Japanese Laid-open Patent Publication No. 2009-282916
In order to calculate clock jitter of a clock path, for example, a technique for considering the difference between the maximum path delay and the minimum path delay of the clock path, that is to say, the maximum value of the differences between path delays of the clock path as clock jitter is used. Calculated clock jitter is taken into consideration at design time. However, if clock jitter is overestimated, the difficulty of designing a semiconductor integrated circuit which meets required specifications may increase. In addition, as a result, turn around time (TAT) for design may lengthen.